ESP-IDF Firmware
Firmware architecture and call graph
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aes3_tie_log.c
Go to the documentation of this file.
1/*
2 * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include "dsp_common.h"
8#include <stdarg.h>
9
10#define TIE_LOG_ENABLED 1
11
12#if (CONFIG_IDF_TARGET_ESP32S3)
13
14esp_err_t tie_log(int n_regs, ...)
15{
16
17#if !TIE_LOG_ENABLED
18 return ESP_OK;
19#else
20
21 va_list list;
22 va_start(list, n_regs);
23
24 uint32_t reg_128_bits[4] = {0, 0, 0, 0};
25 int reg_code;
26
27 for (int i = 0; i < n_regs; i++) {
28 reg_code = va_arg(list, int);
29
30 // ACCX register
31 if ( reg_code == 'a') {
32 asm volatile("rur.accx_0 %0" : "=a" (reg_128_bits[0]));
33 asm volatile("rur.accx_1 %0" : "=a" (reg_128_bits[1]));
34 printf("ACCX - %02x %08x", (unsigned int)reg_128_bits[1], (unsigned int)reg_128_bits[0]);
35 printf(" --- %llu\n", (long long unsigned)reg_128_bits[1] << 32 | (unsigned int)reg_128_bits[0]);
36 }
37
38 // SAR:_BYTE register
39 else if ( reg_code == 's') {
40 asm volatile("rur.sar_byte %0" : "=a" (reg_128_bits[0]));
41 printf("SAR_BYTE - %d\n", (unsigned int)reg_128_bits[0]);
42 }
43
44 // Q0 - Q7 registers
45 else if ((reg_code >= 0) && (reg_code <= 7)) {
46 switch (reg_code) {
47 case 0 : {
48 asm volatile("ee.movi.32.a q0, %0, 0" : "=a" (reg_128_bits[0]));
49 asm volatile("ee.movi.32.a q0, %0, 1" : "=a" (reg_128_bits[1]));
50 asm volatile("ee.movi.32.a q0, %0, 2" : "=a" (reg_128_bits[2]));
51 asm volatile("ee.movi.32.a q0, %0, 3" : "=a" (reg_128_bits[3]));
52 printf("Q0");
53 break;
54 }
55 case 1 : {
56 asm volatile("ee.movi.32.a q1, %0, 0" : "=a" (reg_128_bits[0]));
57 asm volatile("ee.movi.32.a q1, %0, 1" : "=a" (reg_128_bits[1]));
58 asm volatile("ee.movi.32.a q1, %0, 2" : "=a" (reg_128_bits[2]));
59 asm volatile("ee.movi.32.a q1, %0, 3" : "=a" (reg_128_bits[3]));
60 printf("Q1");
61 break;
62 }
63 case 2 : {
64 asm volatile("ee.movi.32.a q2, %0, 0" : "=a" (reg_128_bits[0]));
65 asm volatile("ee.movi.32.a q2, %0, 1" : "=a" (reg_128_bits[1]));
66 asm volatile("ee.movi.32.a q2, %0, 2" : "=a" (reg_128_bits[2]));
67 asm volatile("ee.movi.32.a q2, %0, 3" : "=a" (reg_128_bits[3]));
68 printf("Q2");
69 break;
70 }
71 case 3 : {
72 asm volatile("ee.movi.32.a q3, %0, 0" : "=a" (reg_128_bits[0]));
73 asm volatile("ee.movi.32.a q3, %0, 1" : "=a" (reg_128_bits[1]));
74 asm volatile("ee.movi.32.a q3, %0, 2" : "=a" (reg_128_bits[2]));
75 asm volatile("ee.movi.32.a q3, %0, 3" : "=a" (reg_128_bits[3]));
76 printf("Q3");
77 break;
78 }
79 case 4 : {
80 asm volatile("ee.movi.32.a q4, %0, 0" : "=a" (reg_128_bits[0]));
81 asm volatile("ee.movi.32.a q4, %0, 1" : "=a" (reg_128_bits[1]));
82 asm volatile("ee.movi.32.a q4, %0, 2" : "=a" (reg_128_bits[2]));
83 asm volatile("ee.movi.32.a q4, %0, 3" : "=a" (reg_128_bits[3]));
84 printf("Q4");
85 break;
86 }
87 case 5 : {
88 asm volatile("ee.movi.32.a q5, %0, 0" : "=a" (reg_128_bits[0]));
89 asm volatile("ee.movi.32.a q5, %0, 1" : "=a" (reg_128_bits[1]));
90 asm volatile("ee.movi.32.a q5, %0, 2" : "=a" (reg_128_bits[2]));
91 asm volatile("ee.movi.32.a q5, %0, 3" : "=a" (reg_128_bits[3]));
92 printf("Q5");
93 break;
94 }
95 case 6 : {
96 asm volatile("ee.movi.32.a q6, %0, 0" : "=a" (reg_128_bits[0]));
97 asm volatile("ee.movi.32.a q6, %0, 1" : "=a" (reg_128_bits[1]));
98 asm volatile("ee.movi.32.a q6, %0, 2" : "=a" (reg_128_bits[2]));
99 asm volatile("ee.movi.32.a q6, %0, 3" : "=a" (reg_128_bits[3]));
100 printf("Q6");
101 break;
102 }
103 case 7 : {
104 asm volatile("ee.movi.32.a q7, %0, 0" : "=a" (reg_128_bits[0]));
105 asm volatile("ee.movi.32.a q7, %0, 1" : "=a" (reg_128_bits[1]));
106 asm volatile("ee.movi.32.a q7, %0, 2" : "=a" (reg_128_bits[2]));
107 asm volatile("ee.movi.32.a q7, %0, 3" : "=a" (reg_128_bits[3]));
108 printf("Q7");
109 break;
110 }
111 }
112
113 printf(" - 0x%08X %08X %08X %08X --- ", (unsigned int)reg_128_bits[3], (unsigned int)reg_128_bits[2], (unsigned int)reg_128_bits[1], (unsigned int)reg_128_bits[0]);
114 printf("%u %u %u %u %u %u %u %u\n", (unsigned int)reg_128_bits[3] >> 16, (unsigned int)reg_128_bits[3] & 0x0000FFFF,
115 (unsigned int)reg_128_bits[2] >> 16, (unsigned int)reg_128_bits[2] & 0x0000FFFF,
116 (unsigned int)reg_128_bits[1] >> 16, (unsigned int)reg_128_bits[1] & 0x0000FFFF,
117 (unsigned int)reg_128_bits[0] >> 16, (unsigned int)reg_128_bits[0] & 0x0000FFFF);
118 } else {
119 printf("Bad register code");
120 }
121 }
122 printf("------------------------------------------------------------------------------------\n");
123
124 return ESP_OK;
125#endif //TIE_LOG_ENABLED
126}
127
128#endif // CONFIG_IDF_TARGET_ESP32S3
esp_err_t tie_log(int n_regs,...)
Logginng for esp32s3 TIE core Registers covered q0 to q7, ACCX and SAR_BYTE.
int esp_err_t
Definition esp_err.h:21
#define ESP_OK
Definition esp_err.h:23