ESP-IDF Firmware
Firmware architecture and call graph
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dsps_fft4r_platform.h
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1#ifndef _dsps_fft4r_platform_H_
2#define _dsps_fft4r_platform_H_
3
4#include "sdkconfig.h"
5
6#ifdef __XTENSA__
7#include <xtensa/config/core-isa.h>
8#include <xtensa/config/core-matmap.h>
9
10
11#if ((XCHAL_HAVE_FP == 1) && (XCHAL_HAVE_LOOPS == 1))
12
13#define dsps_cplx2real_fc32_ae32_enabled 1
14
15#endif //
16
17
18#if ((XCHAL_HAVE_LOOPS == 1) && (XCHAL_HAVE_MAC16 == 1))
19
20#define dsps_fft2r_sc16_ae32_enabled 1
21
22#endif //
23
24#if (XCHAL_HAVE_LOOPS == 1)
25
26#define dsps_bit_rev_lookup_fc32_ae32_enabled 1
27
28#endif //
29#endif // __XTENSA__
30
31#if CONFIG_IDF_TARGET_ESP32P4
32#ifdef CONFIG_DSP_OPTIMIZED
33#define dsps_fft4r_fc32_arp4_enabled 1
34#else // CONFIG_DSP_OPTIMIZED
35#define dsps_fft4r_fc32_arp4_enabled 0
36#endif // CONFIG_DSP_OPTIMIZED
37#endif
38
39#if CONFIG_IDF_TARGET_ESP32
40#ifdef CONFIG_DSP_OPTIMIZED
41#define dsps_fft4r_fc32_ae32_enabled 1
42#else // CONFIG_DSP_OPTIMIZED
43#define dsps_fft4r_fc32_ae32_enabled 0
44#endif // CONFIG_DSP_OPTIMIZED
45#endif
46
47#if CONFIG_IDF_TARGET_ESP32S3
48#ifdef CONFIG_DSP_OPTIMIZED
49#define dsps_fft4r_fc32_aes3_enabled 1
50#else // CONFIG_DSP_OPTIMIZED
51#define dsps_fft4r_fc32_aes3_enabled 0
52#endif // CONFIG_DSP_OPTIMIZED
53#endif
54
55#endif // _dsps_fft4r_platform_H_